1. Field of the Invention
The present invention relates to an information processing apparatus and an information processing method.
2. Related Background Art
In recent years, operation speed of a CPU (central processing unit) and capacities of an IC memory and a hard disk increase, whereby also an amount of data to be handled and processed by an information processing apparatus increases. Based on such an increase in the data amount, an amount of data to be transmitted and transferred among various blocks provided inside the information processing apparatus necessarily increases.
Incidentally, the related background art will be explained by taking an information processing apparatus of handling and processing image data as a representative example of an apparatus for handling and processing a large amount of data.
That is, such an image data processing apparatus roughly includes a portion which consists of a CPU, an IC memory and a hard disk for generally storing and processing the image data, and a hardware portion which completes the image process which could not be completely processed by the CPU during a required time. Here, the former portion has the structure being common to that of a general computer, whereby the same architecture as that in the general computer is applied to the former portion. Then, the latter portion (hardware portion) is added to the former portion.
Besides, in the image process, generally plural kinds of processes are performed to one image data. For example, color image data can be represented in various color spaces such as an RGB color space, a YUV color space, an Lab color space, a CMYK color space, and the like. Therefore, the color image data in a certain color space is input and processed in one image process, whereby it is necessary to convert the color space of the input color image data into a proper color space necessary in the image process. Moreover, the processed color image data is then converted into color image data in a desired color space, whereby, in such a case, the three kinds of processes (color space conversion, certain image process, and color space conversion) are sequentially performed in regard to the one image data.
FIG. 4 is a block diagram showing a conventional image processing apparatus. In FIG. 4, a master block 1 has the same structure as that of the general computer, in which a CPU 11 and a memory unit 12 are connected to each other by means of a data transmission path 13. On one hand, a slave block 2 includes an image processing unit 23 which achieves an image process independently of the CPU 11. The master block 1 and the slave block 2 are connected to each other by means of a data transmission path 3 through an I/F (interface) unit 10 and a packet selector 21. Moreover, the slave block 2 and a slave block 2′ are connected to each other by means of a data transmission path 3′ through a packet deselector 24 of the slave block 2 and the packet selector of the slave block 2′, and then a last slave block 2″ and the master block 1 are connected to each other by means of a data transmission path 4 through the packet deselector of the slave block 2″ and the I/F unit 10 of the master block 1. Here, it should be noted that the block diagram shown in FIG. 4 is made simple for the sake of convenience in explanation, that is, the actual structure of the image processing apparatus is of course more complex.
FIG. 5 is a diagram for explaining the unit of data process to be performed by the image processing apparatus. As shown in FIG. 5, since an enormous amount of data are necessary for one image data, the one image data is divided into plural tiles each having a certain size so that the image processing unit 23 can easily process it. Moreover, in order to suppress or control the capacity of the memory unit 12 and also enable it to store the data of a large number of images, the data is stored in each tile in compressed form. The compressed image data on the tile is treated as a unit of process, whereby it is necessary to obtain the information representing, e.g., which tile (portion) in which image the compressed image data belongs to. Therefore, the data which consists of the obtained information as a header portion and the compressed image data as a data portion is treated as the actual unit of process, and this unit of process is called a packet.
In addition to the information representing which image the packet concerns and the information representing which portion of the image the tile concerns, the header portion of the packet includes information representing a kind of image data (e.g., color image data or black-and-white image data), information representing a used color space if the used data is the color image data, and the like. Moreover, in addition to the information concerning the image itself, the-header portion of the packet includes information for designating what kind of image process should be performed to which block (i.e., block designation, and process designation).
FIG. 6 is a block diagram showing the internal structure of the I/F unit 10, and FIG. 7 is a block diagram showing the internal structure of the packet selector 21.
As shown in FIG. 6, the I/F unit 10 consists of a DMAC (direct memory access controller) 101 which reads the packet from a designated area of the memory unit 12 and sends the read packed to the data transmission path 3 without using the CPU 11, and a DMAC 102 which receives the packet sent from the data transmission path 4 and writes the received packet in a designated area in the memory unit 12 without using the CPU 11.
Moreover, as shown in FIG. 7, the packet selector 21 monitors the header portion of the packet sent from the data transmission path 3, and compares the block designation of the monitored head portion with a value (“X” in this case) of block discrimination setting 25. Then, the packet selector 21 controls a selector 212 so as to send the packet to a data transmission path 22 and otherwise sort or distribute the packet to appropriate image processing units 23 according to the process designation of the header portion, when the block designation of the head portion is not equal to the value of the block discrimination setting 25. Therefore, when the block designation of the header portion of the sent packet is different from the own block discrimination setting, the packet in question is sent to a next block as it is through the data transmission path 22.
The image processing unit 23 processes the input packet and then outputs the packet as the result of the process. At that time, the block designation and the process designation of the header portion of the output packet corresponding to the image processing unit 23 in question are deleted, or a process-end flag is set.
By doing so, the packet sent from the master block 1 is sequentially subjected to the necessary processes based on block discrimination settings 25′, . . . , and 25″ by the slave blocks 2, 2′, . . . , and 2″ through the data transmission paths 3′, . . . , and 3″ respectively, and then the processed packet is returned to the master block 1 through the data transmission path 4.
However, in the above related background art, because the block discrimination of the slave block is fixedly set, it is necessary to again allocate the block discrimination and to change software to be executed by the CPU 11 even in a similar system of which the number of slave blocks is different.